The present inventive subject matter herein relates to semiconductor memory devices and methods of operation thereof and, more particularly, to nonvolatile memory devices and methods of operation thereof.
Generally, semiconductor memory devices may be classified as volatile memory devices and nonvolatile memory devices. Volatile memory devices typically lose stored data when not powered, while nonvolatile memory devices typically can maintain stored data even when not powered. Nonvolatile memory devices such as flash memory, ferroelectric RAM (FRAM), magnetic RAM (MRAM) and phase change RAM (PRAM), may include various types of memory cell transistors.
Flash memory devices may be classified as NOR type flash memory devices and NAND flash memory devices according to a cell array structure. In NOR type flash memory devices, memory cell transistors are independently connected to bit lines and word lines. NOR type flash memory device may have superior random access time characteristics. In contrast, in NAND type flash memory devices, a plurality of memory cell transistors is serially connected in a structure referred to as a cell string. Typically, one bit line contact is needed per one cell string. Thus, the NAND type flash memory devices may allow for a higher degree of integration.
Flash memory devices typically include a memory cell array storing data. The memory cell array may include a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. Each of the pages may include a plurality of memory cells. The memory cells may be selectively in “on” and “off” states according to threshold voltage distribution. A cell in an “on” state may be considered an erased cell and a cell in an “off” state may be a programmed cell. Because of structural characteristics, flash memory devices may perform an erase operation by memory block units and perform read or write operations by page units.
Flash memory devices commonly have a cell string structure, wherein a cell string includes a string select transistor (SST) connected to a string select line (SSL), memory cells connected to a plurality of word lines (WL) and a ground select transistor (OST) connected to a ground select line (GSL). The string select transistor (SST) may be connected to a bit line and the ground select transistor (GST) may be connected to a common source line (CSL).
A noise voltage generated on the common source line (CSL) may cause a malfunction of the flash memory devices. For example, although a specific memory cell is not sufficiently programmed (or written), it may be verified as being programmed. Because of the malfunction, when reading the cell after a program operation is finished, the cell may be erroneously read to be a programmed memory cell instead of an erased cell.